Search - memory vhdl

[Other resource] vhdl程序例子

Description: vhdl程序源代码，包括Combinational Logic Counters Shift Registers Memory State Machines Registers Systems ADC and DAC Arithmetic等-VHDL source code, including Combinational Logic Counters Shift Registers State Machines Registers Memory Systems ADC and DAC Arithmetic etc.
Platform: | Size: 169419 | Author: 王力 | Hits:

[Other resource] my_ramlib_06

Description: 包括各种类型存储器的VHDL描述，如FIFO，双口RAM等 -including various types of memory VHDL description, such as FIFO, Dual Port RAM, etc.
Platform: | Size: 616055 | Author: ruan | Hits:

[WEB Code] vhdl

Description: This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examp terms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any synthesised using current synthesis tools.
Platform: | Size: 173517 | Author: gbj | Hits:

[VHDL-FPGA-Verilog] VHDL 语言例程集锦

Description: 包括很多有用的VHDL源代码，如下。文件为PDF格式，可以直接copy你想要的部分，然后粘贴到你自己的VHDL文件中。能帮你节省很多开发时间。 1.Combinational Logic 2.Counters 3.Shift Registers 4.Memory 5.State Machines 6.Registers 7.Systems 8.ADC and DAC 9.Arithmetic
Platform: | Size: 169165 | Author: bigchance@126.com | Hits:

[Other] sdram32

Description: sram 存储器控制程序很完整，值得认真研究，很有帮组-SRAM memory control program is very complete, worthy of serious study, is to help groups
Platform: | Size: 23552 | Author: 许曲 | Hits:

[Embeded-SCM Develop] memoire_alphabet

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器。实现memory存储。-Altera NIOS processor experiments QUARTUS using VHDL compiler into processors. Achieving memory storage.
Platform: | Size: 1024 | Author: 秦拣俭 | Hits:

[VHDL-FPGA-Verilog] EvsStore

Description: 用VHDL编写的由FPGA控制SDRAM的存储控制程序-VHDL prepared by the FPGA control SDRAM memory control procedures
Platform: | Size: 1024 | Author: | Hits:

[OS Develop] ARM_00_OS

Description: 看看ARM菜鸟在ARM7上写的操作系统——ARM圈圈操作系统最近在ADuC7027上写了一个ARM_00_OS，头都写晕了，发上来给大家一起来看看。任务按优先级调度，如果处于就绪态且优先级最高的任务有两个或更多，则按时间片轮循调度。支持任务创建、任务删除、内存分配、简单的消息、简单的设备管理、CPU及内存等使用统计等功能。任务可处于ARM模式或THUMB模式，在创建任务时，要指定任务所处于的模式。从这里下载整个文件包：http://blog.21ic.com/more.asp?name=computer00&id=16341 -look at birdie in ARM ARM7 written in the operating system-- the operating system ARM circle recently in ADu C7027 write a ARM_00_OS, write head dizzy, deputy undersecretary for everyone to see. Tasks according to priority scheduling, in place if the state but the highest priority tasks of two or more, according to the time-Round Robin scheduling. Support mission to create, delete tasks, memory allocation, the simple information, a simple device management, CPU and memory usage statistics capabilities. At tasks THUMB ARM model or models in the creation mandate, the mandate should be designated at a model. From here to download the whole package : http :// blog.21ic.com/more.asp name = computer00
Platform: | Size: 360448 | Author: Computer00 | Hits:

[VHDL-FPGA-Verilog] VHDL_Memory_Library_Code

Description: 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
Platform: | Size: 23552 | Author: Jawen | Hits:

[VHDL-FPGA-Verilog] byvhdstopwatchl

Description: 1.高精度数字秒表（0.01秒的vhdl语言实现） 2.具有定时，暂停，按键随机存储，翻页回放功能； 3.对30M时钟分频产生显示扫描时钟 4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔，可控性高。 5.模块化设计，其中的许多函数可以成为vhdl语言的通用经典例子（包含分频电路设计，动态扫描时钟设计，译码电路设计，存储器设计，存储回放显示设计）-1. High-precision digital stopwatch (0.01 seconds vhdl language) 2. With a timer, suspended Random memory keys, flip playback function; 3. right 30M clock frequency scan have revealed four clock. Precision high 0.01s and and can be changed to alter the frequency than the frequency interval and Hutchison, controlled high. 5. Modular design, Many of these functions can become the common language vhdl classic examples (including sub-frequency circuit design, Dynamic scanning clock design, decoding circuit design, memory design, storage intervals showed Design)
Platform: | Size: 2048 | Author: 方周 | Hits:

[Embeded-SCM Develop] VHDLRAM

Description: 介绍vhdl硬件描述语言的特点及设计思想，运用vhdl硬件描述语言实现计算机原理实验中RAM存储器的设计方法，重点描述了对传统计算机组成原理实验中移植到基于CPLD平台的思想-introduced vhdl hardware description language features and design ideas, vhdl use hardware description language computer science experiments RAM memory design, Description of key computer components of the traditional principle experiment to transplant platform based on the idea of CPLD
Platform: | Size: 30720 | Author: 刘浏 | Hits:

[Embeded-SCM Develop] dualportRAM

Description: 双端口RAM的VHDL语言实现。完全在CPLD芯片上测试通过。可以实现对存储器读操作的同时对另外一个空间写操作-dual-port RAM VHDL. Totally CPLD chip test. Memory can be achieved right time to operate while the other was a space operation
Platform: | Size: 90112 | Author: 王雪松 | Hits:

[VHDL-FPGA-Verilog] RS_5_3_GF256

Description: 用于NAND FLASH CONTROLLER 中的 ecc 各个模块VHDL代码-NAND FLASH CONTROLLER for ecc modules in VHDL code
Platform: | Size: 197632 | Author: 陈佳宜 | Hits:

[VHDL-FPGA-Verilog] mem_ctrl_latest.tar

Description: 存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
Platform: | Size: 331776 | Author: zhangsan | Hits:

[VHDL-FPGA-Verilog] dpmem2clk.tar

Description: Dual port memory VHDL/Verilog design
Platform: | Size: 3072 | Author: Ravi | Hits:

[Other] Memory

Description: 计算机组成原理简单的存储器程序，仅供大家参考。-Principles of Computer Organization simple memory procedures, only reference.
Platform: | Size: 233472 | Author: 于洪宇 | Hits:

[Other] P6_Cache

Description: MEMORY CACHE SIMPLE CODE
Platform: | Size: 12847104 | Author: anaterremoto | Hits:

[Software Engineering] OneNAND_in_embed_sys

Description: OneNAND闪存在嵌入式系统中的应用 OneNAND Flash是三星公司开发的一类Flash芯片，它克服了传统NAND Flash接口复杂的缺点，具有接口简单、读写速度快、容量大、寿命长、成本低等优点。文章从软硬件两方面介绍了其在嵌入式系统中的应用，特别是逻辑块和物理块地址的映射、读写擦操作、坏块处理、性能优化等技术。-OneNAND flash memory in embedded system applications developed by Samsung' s OneNAND Flash is a type Flash chips, which overcomes the traditional shortcomings of NAND Flash interface, a complex with a simple interface, read and write speed, large capacity and long life and low cost advantages. The article describes both hardware and software in embedded system applications, in particular logical block and physical block address mapping, read and write wiping operation, bad block handling, performance optimization technologies.
Platform: | Size: 48128 | Author: zhangdong | Hits:

[VHDL-FPGA-Verilog] i28f128p30

Description: Intel Strata Flash Memory (P30)接口控制器的VHDL源代码-Intel Strata Flash Memory (P30) interface controller of the VHDL source code
Platform: | Size: 18432 | Author: wangyu | Hits:

[Industry research] 2.-Memory-a-VHDL

Description: This consists of Memory & VHDL programming knowledge.
Platform: | Size: 463872 | Author: Parikshit | Hits:

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